1. Field of the Invention
The present invention relates to a layout method of a semiconductor integrated circuit, particularly for an automatic layouting method and a program for generating layout data of a semiconductor integrated circuit, and a method for manufacturing a semiconductor integrated circuit with optical proximity correction.
2. Description of the Related Art
Along with the miniaturization of elements such as transistors or interconnects used in semiconductor integrated circuits, the size of element has become smaller than light source wavelengths used for an aligner. In such cases, during a photolithography process or an etching process, the planar shape of an element pattern in the periphery of an element to be formed adversely affects the planar shape of the element pattern to be formed. As a result, it is difficult to form the element pattern on a wafer according to a design pattern. Therefore, optical proximity correction (OPC) has been performed so as to add a correction pattern to the design pattern in advance so that the planar shape of the formed element pattern can assume a desired shape.
When carrying out OPC to generate a cell mask pattern, lithography simulation and the like is performed based on the generated mask pattern so as to calculate the planar shape of an element pattern to be formed on the wafer. Conditions for OPC are then set so that differences in dimension between the planar shapes of the generated mask patterns and the planar shapes of the calculated element patterns can fall within a desired range of differences in dimension (hereafter referred to as ‘dimensional tolerance’). OPC is then carried out for cells under the set conditions for OPC, thereby generating a cell pattern. Required conditions for the dimensional tolerance are hereafter referred to as ‘dimensional tolerance conditions’.
In the case of recent highly integrated elements and interconnects, the stricter the dimensional tolerance conditions, namely, the smaller the dimensional tolerances are set, the more the planar shape of the element pattern formed on the wafer resembles the planar shape of the design element pattern. However, the mask pattern generally has more places that need to be corrected through OPC as the dimensional tolerance conditions become stricter. Accordingly, the time required for OPC increases. The greater the dimensional tolerances are set by relaxing dimensional tolerance conditions, the more the time required for OPC decreases. However, in the case of carrying out OPC by relaxing dimensional tolerance conditions, the difference between the planar shape of an element pattern formed on the wafer and the planar shape of the design pattern increases. Therefore, the difference between characteristics of the actually manufactured element and characteristics of the desired element increases. As a result, characteristics of semiconductor integrated circuits are impaired and desired characteristics are unsatisfied, thereby reducing the yield ratio.